There is a continuing goal to produce highly-integrated, high-speed, low-power memory devices. Traditional memory devices are static random access memory (SRAM) and dynamic random access memory (DRAM). SRAM can operate at high speeds, but typically consumes a relatively large amount of semiconductor real estate relative to other types of memory. DRAM traditionally comprises a transistor and a capacitor, and individual DRAM unit cells can be formed to consume relatively small amounts of semiconductor real estate as compared to SRAM cells. However, even DRAM is becoming too large for next generation levels of integration, because it is becoming increasingly difficult to create satisfactory capacitors with increasing levels of integration.
There is currently substantial interest in a new type of capacitor-less DRAM (also referred to as a floating body cell) that may be able to achieve much higher levels of integration than the traditional DRAM that utilized a capacitor. The new memory uses a floating body of a partially or fully depleted silicon on insulator (SOI) field effect transistor (FET) as a storage node, instead of using a storage capacitor.
It would be desirable to develop floating body cells which can be readily incorporated into semiconductor fabrication processes. It would also be desirable to develop memory arrays using floating body cells, and to develop methods for forming such arrays.
Although the methods and structures described herein were developed, at least in pall, for integration of floating body cells; it is to be understood that the invention can have additional applications.